1. Field of the Invention
The present invention relates to a phase synchronizing circuit for use with a scanning converter for converting a scanning speed, a data transmission speed converter for exchanging data of a serial digital picture signal of a television signal, and a scanning circuit for securely scanning a picture signal without fluctuation.
2. Description of the Related Art
FIG. 8 is a block diagram showing a phase synchronizing circuit for use with a communication system that can transmit serial data at high speed.
In FIG. 8, the phase synchronizing circuit is composed of a data input terminal 51, an input clock input terminal 52, a data output terminal 53, an output clock input terminal 54, a register 55, an input side counter 56, an output side counter 57, a selection output circuit 58, and a clock phase comparing circuit 59.
A serial data signal is supplied to the data input terminal 51. Next, the serial data signal is supplied to the register 55. The register 55 is composed of a plurality of flip-flop circuits (hereinafter, referred to as F/F) that are connected in parallel. The F/Fs successively store the serial data of the input data. The period of which one F/F updates data depends on the stage number of F/Fs. For example, when the register 55 is composed of 10 stages of F/Fs, the data update period of each F/F becomes 1/10 period. Thus, the input data is chronologically expanded 10 times. The selection output circuit 58 selects one F/F output data from the F/Fs composing the register 55 corresponding to a selection signal 62 received from the output side counter 57 and supplies the data to the data output terminal 53.
A clock signal in synchronization with the input data is supplied to the clock input terminal 52. The input side counter 56 generates frequency-divided clock signals with phases that differ by one clock period and supplies the frequency-divided clock signals as write clock signals to the register 55. In addition, the input side counter 56 supplies a write phase signal 61 to the clock phase comparing circuit 59.
The output side counter 57 generates 10 frequency-divided clock signals with phases that differ by one clock period with an output clock signal received from the output clock input terminal 54 and outputs the frequency-divided clock signals as selection signals to the selection output circuit 58. In addition, the output side counter 57 supplies a phase reference signal 63 to the clock phase comparing circuit 59. The clock phase comparing circuit 59 detects the phase difference between the write phase signal 61 and the phase reference signal 63. When the clock phase comparing circuit 59 cannot detect a predetermined phase difference, it supplies a reset signal 64 to the input side counter 56 so as to change the phases of the write frequency-divided clock signals 60 of the input side counter 56 to the initial state.
When the phase synchronizing circuit is used for a serial digital picture signal (hereinafter, referred to as picture signal), the input side counter 56 is reset while a picture is being displayed. Thus, a noise takes place in the output picture due to the fact that the conventional phase synchronizing circuit is mainly used for high speed communication systems and the phase of the input clock signal does not chronologically vary. Further, it is generally not necessary to reset the unit once the unit is in operation after the initial reset. Even if the reset operation is required, the number of times thereof is small. Thus, such a high speed communication system does not have a function for controlling the timing of the reset operation.
However, in the case where the input signal is a picture signal, the reset operation may be frequently required. For example, it is necessary for a picture signal in a broadcasting station to synchronize with a reference signal called a black burst signal. An operation clock signal is made from the black burst signal. The clock signal is generated by a PLL circuit. However, the phase of the clock signal inevitably fluctuates (this fluctuation is known as jitter) at any time for the principal of the PLL circuit.
In addition, the black burst signal that is the reference signal is an analog signal. Thus, when the black burst signal is supplied to each unit, noise enters the black burst signal and distortion thereof takes place. Consequently, since the jitter takes place, it is estimated that the phase difference between the write clock signal and the read clock signal of the phase synchronizing circuit fluctuates for several clock periods. Thus, when the conventional phase synchronizing circuit is used for a picture signal, the reset operation is frequently performed. When the reset operation is performed while a picture is being displayed, noise takes place in the picture signal.